Across all sectors, industries, and geographies, demands continue for the electronic industry to provide products that are lighter, faster, smaller, multi-functional, more reliable, and more cost-effective. In order to meet these expanding requirements of so many and varied consumers, more electrical circuits need to be more highly integrated to provide the functions demanded. Across virtually all applications, there continues to be growing demand for reducing size, increasing performance, and improving features of integrated circuits.
The seemingly endless restrictions and requirements are no more visible than with products in our daily lives. Smaller and denser integrated circuits are required in many portable electronic products, such as cell phones, portable computers, voice recorders, etc. as well as in many larger electronic systems, such as cars, planes, industrial control systems, etc.
As the demand grows for smaller electronic products with more features, manufacturers are seeking ways to include more features as well as reduce the size of the integrated circuits. However, increasing the density of integration in integrated circuits may be expensive and have technical limitations. Though technology continues its growth to once unimagined extents, practical limits of individual integrated circuits do exist.
To meet these needs, three-dimensional type integrated circuit packaging techniques have been developed and used. Packaging technologies are increasingly using smaller footprints with more circuits in three-dimensional packages. In general, package stacks made by stacking packages and stacked chip packages made by stacking chips in a package have been used.
A Package-on-Package (PoP), as its name implies, is a semiconductor packaging innovation that involves the stacking of two or more packages on top of one another. The PoP is a three dimensional (3D) package in which a fully tested package, such as single die Ball-Grid-Array (BGA) or stacked die BGA (typically memory die), is stacked on a bottom PoP package which usually contains a logic device or logic device combination (logic plus logic, logic plus analog, etc.).
In standard PoP package designs, the top PoP package is interconnected to the bottom PoP package through solder balls around the periphery of the bottom PoP package.
The conventional vertically stacked multi-chip packages require space for forming electrical connections, such as with bond wires, and typically the space is formed by spacers, such as a blank silicon die or an interposer between the packages. These spacers limit the amount of height reduction possible. Conventional PoP configurations require space for package integration and/or stack, also limiting the reduction of the multi-chip package height.
The Fan-in Package-on-Package (Fi-PoP) package system allows stacking multiple logic, analogy, and memory devices in the bottom PoP package. The Fi-PoP package system structure allows for smaller conventional memory packages to be mounted with center ball grid array patterns on the top PoP package.
The Fi-PoP package system also accommodates larger die sizes in a reduced footprint as compared to conventional PoP designs. The footprint reflects what is typically the maximum dimension of the package, namely, the x-y dimension of the package in the horizontal plane.
The Fi-PoP accommodates multiple die and larger die sizes in a reduced footprint. The Fi-PoP package system has an interposer stacked onto a die or a premolded package and has bond wire interconnects to connect between the interposer and the bottom base carrier.
There are two versions of Fi-PoP with one version incorporating a fully-tested internal stacking module package for integration of fully tested memory or other device types within the bottom package. The second version integrates probed good or known good die stacked in the bottom package. Conventional memory packages can be stacked on top of either Fi-PoP design during the board mount process.
Multiple logic, analog, and memory devices can be stacked in the bottom of the Fi-PoP package. Smaller, conventional memory packages with center BGA patterns can be stacked on top, due to an exposed array of land pads on the top, center surface of the package.
The interconnection of the stacked packages can be quite challenging, especially if wire bonding is employed. Aside from the mechanical intricacies involved in managing the complex lay-out of hundreds of microscopic wires subject to loop profile restrictions, cross-talk during device operation must likewise be avoided.
Wire bonding is an electrical conductive structure that usually routes on the side of the stacked package system thus resulting in increased footprint.
Another drawback with the wire bonding in stacked packages is “wire sweep”. Wire sweep results when a wave front of dielectric (commonly a silicon-filled polymer) encapsulation material moving through a mold cavity across the semiconductor die and carrier substrate assembly forces wire bonds to contact adjacent wire bonds and become fixedly molded in such a contacted position after the encapsulation material sets.
When wire sweep occurs, a wire bond of an integrated circuit die to a carrier substrate creates a short circuit, which results in a nonfunctional integrated circuit die assembly.
Generally, the conventional PoP package has a spacer die and any void or delamination in any of the die attach layers will result in locally increased thermal resistance, consequently may cause overheating, and finally might result even in ruining the device.
Thus, a need still remains for a stacked package-on-package system to provide smaller footprint, improved reliability while eliminating the bond wires at the stacking interface and eliminating the die spacer that may cause voids during the die attach process. In view of the ever-increasing need to minimize the size and the total height of the stacked package system, it is increasingly critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.